module vct_arr_6662 (Z, X, Y);
	
	input [5:0] Y;
	input [5:0] X;
	output [5:0] Z;
	

	wire [5:0] P0;
	wire [5:0] carry1;
	wire [5:0] sum1;
	wire [5:0] P1;
	wire [5:0] carry2;
	wire [5:0] sum2;
	wire [5:0] P2;
	wire [5:0] carry3;
	wire [5:0] sum3;
	wire [5:0] P3;
	wire [5:0] carry4;
	wire [5:0] sum4;
	wire [5:0] P4;
	wire [5:0] carry5;
	wire [5:0] sum5;
	wire [5:0] P5;
	wire [5:0] carry6;
	wire [5:0] sum6;


	// generate the partial products.
	and pp1(P0[5], X[5], Y[0]);
	and pp2(P0[4], X[4], Y[0]);
	and pp3(sum1[5], X[5], Y[1]);
	and pp4(P1[4], X[4], Y[1]);
	and pp5(P1[3], X[3], Y[1]);
	and pp6(carry1[2], X[2], Y[1]);
	and pp7(sum2[5], X[5], Y[2]);
	and pp8(P2[4], X[4], Y[2]);
	and pp9(P2[3], X[3], Y[2]);
	and pp10(P2[2], X[2], Y[2]);
	and pp11(carry2[1], X[1], Y[2]);
	and pp12(sum3[5], X[5], Y[3]);
	and pp13(P3[4], X[4], Y[3]);
	and pp14(P3[3], X[3], Y[3]);
	and pp15(P3[2], X[2], Y[3]);
	and pp16(P3[1], X[1], Y[3]);
	and pp17(carry3[0], X[0], Y[3]);
	and pp18(sum4[5], X[5], Y[4]);
	and pp19(P4[4], X[4], Y[4]);
	and pp20(P4[3], X[3], Y[4]);
	and pp21(P4[2], X[2], Y[4]);
	and pp22(P4[1], X[1], Y[4]);
	and pp23(P4[0], X[0], Y[4]);
	and pp24(sum5[5], X[5], Y[5]);
	and pp25(P5[4], X[4], Y[5]);
	and pp26(P5[3], X[3], Y[5]);
	and pp27(P5[2], X[2], Y[5]);
	and pp28(P5[1], X[1], Y[5]);
	and pp29(P5[0], X[0], Y[5]);

	// Array Reduction
	half_adder  HA1(carry1[4],sum1[4],P1[4],P0[5]);
	specialized_half_adder  SHA1(carry1[3],sum1[3],P1[3],P0[4]);
	full_adder  FA1(carry2[4],sum2[4],P2[4],sum1[5],carry1[4]);
	full_adder  FA2(carry2[3],sum2[3],P2[3],sum1[4],carry1[3]);
	full_adder  FA3(carry2[2],sum2[2],P2[2],sum1[3],carry1[2]);
	full_adder  FA4(carry3[4],sum3[4],P3[4],sum2[5],carry2[4]);
	full_adder  FA5(carry3[3],sum3[3],P3[3],sum2[4],carry2[3]);
	full_adder  FA6(carry3[2],sum3[2],P3[2],sum2[3],carry2[2]);
	full_adder  FA7(carry3[1],sum3[1],P3[1],sum2[2],carry2[1]);
	full_adder  FA8(carry4[4],sum4[4],P4[4],sum3[5],carry3[4]);
	full_adder  FA9(carry4[3],sum4[3],P4[3],sum3[4],carry3[3]);
	full_adder  FA10(carry4[2],sum4[2],P4[2],sum3[3],carry3[2]);
	full_adder  FA11(carry4[1],sum4[1],P4[1],sum3[2],carry3[1]);
	reduced_full_adder  RFA1(carry4[0],P4[0],sum3[1],carry3[0]);
	full_adder  FA12(carry5[4],sum5[4],P5[4],sum4[5],carry4[4]);
	full_adder  FA13(carry5[3],sum5[3],P5[3],sum4[4],carry4[3]);
	full_adder  FA14(carry5[2],sum5[2],P5[2],sum4[3],carry4[2]);
	full_adder  FA15(carry5[1],sum5[1],P5[1],sum4[2],carry4[1]);
	reduced_full_adder  RFA2(carry5[0],P5[0],sum4[1],carry4[0]);

	// Generate lower product bits YBITS 

	// Final Carry Propagate Addition
	//   Generate higher product bits
	half_adder CPA1(carry6[0],Z[0],carry5[0],sum5[1]);
	full_adder CPA2(carry6[1],Z[1],carry5[1],carry6[0],sum5[2]);
	full_adder CPA3(carry6[2],Z[2],carry5[2],carry6[1],sum5[3]);
	full_adder CPA4(carry6[3],Z[3],carry5[3],carry6[2],sum5[4]);
	full_adder CPA5(Z[5],Z[4],carry5[4],carry6[3],sum5[5]);
endmodule